Digital adaptation circuitry and methods for programmable logic devices

ABSTRACT

Equalization of an incoming data signal can be controlled by sampling that signal at times when data values in that signal should be stable (“data samples”) and when that signal should be in transition between successive data values that are different (“transition samples”). A transition sample that has been taken between two successive differently valued data samples is compared to a reference value (which can be one of those two data samples). The result of this comparison can be used as part of a determination as to whether to increase or decrease equalization of the incoming data signal.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of, and claims the benefit of andpriority to, U.S. patent application Ser. No. 11/522,284, filed Sep. 14,2006 (currently pending), which is hereby incorporated by reference inits entirety.

BACKGROUND OF THE INVENTION

When a high-speed signal propagates through a transmission medium suchas a printed circuit board backplane, not all of the frequencycomponents get attenuated equally. In general, high frequency componentsare attenuated more than low frequency components. The result is ISI(inter-symbol interference), which causes jitter in the ideal timing ofa signal.

Equalization is a method to boost the high frequency components morethan the low frequency components. Ideally the frequency response of theequalizer should be the inverse transfer function of the backplane orother transmission medium. The combination of the two transfer functionsshould ideally be flat for the frequencies of interest. The problem isthat there may be many possible combinations of equalization solutions.It may therefore require a lot of time to determine the optimal setting.This is usually through trial and error.

An adaptive equalization block can take the burden off the user anddetermine the optimal setting. An adaptive equalizer includes anequalizer and an adaptation “engine” which chooses one of the possibleequalization curves so that the combination of the two transferfunctions is flat. Because of the benefits of using adaptiveequalization, improvements to adaptive equalizer blocks are always beingsought.

SUMMARY OF THE INVENTION

In accordance with certain aspects of the invention, equalization of anincoming data signal may be controlled by detecting two successivedifferently valued bits in the data signal. When two such bits aredetected, a determination can be made as to whether a transition betweenthose bits is relatively late or relatively early. If the transition isrelatively late, then equalization of the incoming signal can beincreased. If the transition is relatively early, then equalization ofthe incoming signal can be deceased.

In accordance with other aspects of the invention, equalization of anincoming data signal may be controlled by sampling that signal at timeswhen data values in the signal should be stable. This sampling produceswhat may be called data samples. The incoming data signal may also besampled at times when that signal should be in transition betweensuccessive data values that are different from one another. Thissampling produces what may be called transition samples. A transitionsample that has been taken between two successive differently valueddata samples may be compared to a reference value (which can be one ofthe two differently valued data samples). The equalization may becontrolled based on a result of this comparison.

In accordance with still other aspects of the invention, circuitry forequalizing an incoming data signal may include first sampling circuitryfor sampling the incoming data signal at times when data values in thatsignal should be stable. The resulting samples may be referred to asdata samples. The equalizing circuitry may further include secondsampling circuitry for sampling the incoming data signal at times whenthat signal should be in transition between successive data values thatare different from one another. The resulting samples may be referred toas transition samples. The equalizing circuitry may still furtherinclude circuitry for comparing a transition sample (taken between twosuccessive differently valued data samples) to a reference value (whichcan be one of the two successive differently valued data samples). Theequalizing circuitry may still further include equalization controlcircuitry for controlling equalization of the incoming data signal basedon an output of the comparison circuitry.

Further features of the invention, its nature and various advantages,will be more apparent from the accompanying drawings and the followingdetailed description.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a simplified schematic block diagram of a known scheme for anadaptive engine.

FIG. 2 is a simplified schematic block diagram of an illustrativeembodiment of some circuitry in accordance with certain aspects of theinvention.

FIG. 3 is a set of simplified signal waveforms, all plotted against acommon, horizontal time scale. These waveforms are useful inunderstanding operation of the FIG. 2 circuitry.

FIG. 4 is a further set of illustrative, simplified waveforms that areuseful in understanding certain aspects of the invention.

FIG. 5 is a table showing decisions that can be made under variousillustrative signal conditions in accordance with certain aspects of theinvention.

FIG. 6 is a simplified block diagram of illustrative equalizer circuitryin accordance with certain aspects of the invention.

FIG. 7 is a more detailed, but still simplified, block diagram of anillustrative embodiment of a portion of the FIG. 6 circuitry inaccordance with certain aspects of the invention.

DETAILED DESCRIPTION

A known scheme for an adaptive equalization block 10 is shown in FIG. 1.This scheme includes an equalizer filter 20 with control knobs 30 and 50(typically implemented electronically) to change the amount of low andhigh frequency boost. Parameter α changes the amount of low frequencygain, while parameter β changes the amount of high frequency boost fromthe equalizer. (HP stands for high pass.) In addition to the equalizerfilter, the remaining circuits in FIG. 1 comprise the adaptive engine100, which controls the amount of boost via the knobs α and β.

The adaptive scheme in FIG. 1 uses an analog approach to determinewhether the amount of boost is correct. Node A is the output of theequalizer 20, and node B is the output of a reference edge generator150. The reference edge generator outputs an “ideal” edge, which theoutput of the equalizer should try to mimic. The low pass and high passfilters 110, 120, 160, and 170, along with the rectifiers 112, 122, 162,and 172, are used to extract the energy of the signals at nodes A and B.The output of the high pass filter 120 and rectifier 122 on node Aextracts the high frequency energy of the signal after the equalizer 20.The output of the high pass filter 170 and rectifier 172 on node Bextracts the high frequency energy of the signal after the referencegenerator 150. These two levels are then presented to the comparator180, which compares the high frequency energy between the two outputs.The result of the comparison is integrated on capacitor C2 to create ananalog level, which controls the amount of high frequency boost. This ispart of a feedback system, which forces the energies to be equal, andthus the “proper” amount of high frequency boost. This ideally occurswhen the edge rate of the equalizer 20 output is equal to the edge rateof the reference generator 150 output. The amount of low frequency gainis controlled in a similar manner via the low pass filters andrectifiers 110, 112, 160, and 162 in cooperation with comparator 130 andcapacitor C1.

The present disclosure describes an adaptive engine which uses a digitalapproach. Instead of comparing energy levels of the equalizer 20 outputand the output of a reference edge 150, the absolute timing jitter iscompared by a digital phase detector. FIG. 2 shows details of anillustrative digital phase detector 200. FIG. 3 shows the timinggenerated by phase detector 200. The small timing diagram in FIG. 2shows the terminology used. “A”, “B,” and “C” refer to the relativelocations of three consecutive bits A, B, and C, respectively. “ATB” isthe transition point sampled by the phase detector between bits A and B.“BTC” is the transition point sampled between bits B and C. These pointsare sampled by a half rate phase detection scheme. Half rate refers tothe fact that the clock runs at half the rate of the data. Full rateimplies that each rising edge of a clock samples data.

As shown in FIG. 2, the first two columns of flip flops 205 a-d and 210a-d are clocked by a four-phase clock with phases 0, 90, 180, and 270running at half the data rate. These flip flops sample the data andgenerate the outputs DEVEN, DMQ, DODD, and DMQB, respectively. In thetiming diagram these points represent sample points A, ATB, B, and BTC,respectively. In the rest of this discussion we will use theserepresentations interchangeably. The important thing to note is thatDEVEN corresponds to sampling of bit location A. The timing diagram inFIG. 3 shows how this is accomplished. Note that sampling the incomingdata signal at points like A, B, and C corresponds to sampling thatsignal at times when data values in the signal should be stable atbinary 1 or binary 0. Such samples may be referred to as data samples.Sampling the incoming data signal at points like ATB and BTC correspondsto sampling that signal at times when the signal should be in transitionbetween two successive differently valued data bits or data samples.Samples taken at points like ATB and BTC may be referred to astransition samples.

The flip flops 220 a-c that generate outputs D0, DM01 and D1 are clockedby CK90. The purpose of these flip flops is to synchronize A, ATB, and B(or take a snapshot of these bits) and hold the value so that it can beexamined. The flip flops 220 d-f that generate D1D, DM12, and D2synchronize B, BTC, and C and hold the value so that it can be examined.FIG. 4 shows how the outputs of the phase detector can be examined todetermine if the amount of equalization is correct. Also, note in FIG. 4that the binary values 0 and 1 can be interchanged and in the interestof brevity we just discuss one case. For example, we could have replacedall the zeros with ones and vice-versa.

In order that this scheme works properly, this phase detector ispreferably shared with the phase detector used in the receiver clock anddata recovery (CDR) block. This is the same phase detector used by theCDR to properly center the data eye (i.e., to find where sampling pointslike A, B, and C should be in order to be most nearly centered betweentransition locations (like ATB and BTC) in the incoming data signal).Thus, in this disclosure we can assume that clock CK0 samples at theoptimal point of data A, CK90 samples the transition point between bitsA and B and so on. Three timing diagrams in FIG. 4 show what would besampled by the flip flops if the amount of equalization is ideal (topwaveform), too small (bottom waveform), or too large (middle waveform).Note that in the middle waveform in FIG. 4 the transition from A to B isrelatively early (e.g., as compared to the corresponding, properly timedtransition in the top waveform, or as compared to the corresponding,relatively late transition in the bottom waveform). On the other hand,in the bottom waveform in FIG. 4 the transition from A to B isrelatively late (e.g., as compared to the corresponding, properly timedtransition in the top waveform, or as compared to the corresponding,relatively early transition in the middle waveform).

FIG. 5 shows an illustrative example of how to determine theequalization based on the sampled values. A scheme is given based on adifferent sequence of bits detected. In this scheme, an incoming datapattern of 001 (shown by the binary digits in FIG. 4) or 110 (bitsinverted from what is shown by the binary digits in FIG. 4) is detectedand the outputs based on the detected sequence are used to determine theequalization level. As shown in FIG. 5, an over-equalized signal is seenas the transition sample T having the same value as the 2nd data samplebit B (or the complement or inverse of 1st data sample bit A). Anunder-equalized signal, on the other hand, is seen as the transitionsample T looking like the 1st data sample bit A (or the complement orinverse of 2nd data sample bit B). This is just one illustrativeincoming data sequence, and any number of other sequences can bedetected and used to determine if the amount of equalization is toosmall or too large. The point is that a pattern detector is preferablyemployed, and the appropriate sample points are observed to determine ifthe equalization needs to be adjusted. 001 or 110 was chosen as thepattern to be detected in this example because it is a pattern whichallows a signal to “settle” near its final value (in response to thefirst two identical bits), and then a higher frequency component isintroduced (in order to transition to the third, differently valuedbit). The ideal pattern might be one having a relatively long CID(consecutive identical digit) followed by a transition. Thus, a patternsuch as . . . 0000001 . . . or . . . 1111110 . . . would be a goodcandidate. The tradeoff, however, would be that such a long CID mayhappen relatively infrequently, if ever. This might lead to unacceptablylong convergence times. Additionally, most patterns are DC balanced andhave a minimum required transition density that prohibits very longCIDs, an example being 8b10b. The other tradeoff would be that a verylong string of latches would be required to “remember” the data so thatthe pattern is detected.

As mentioned earlier, the phase detection circuitry preferably has thesame timing as the phase detector of the CDR (clock and data recovery)block. Recall that the purpose of the CDR is to extract the clockembedded in a high-speed serial data stream. The CDR extracts a clockand lines up the phase such that it is optimally centered about themiddle of the data for CK0 and CK180. This puts data samples like A, B,and C in FIG. 2 midway between transitions like those at ATB and BTC inthat FIG. Another point is that the CDR is typically a closed loopsystem with a certain bandwidth. Thus, during adaptation the two loopsmay interact. This timing can be important, which means that theadaptive circuitry should either share the phase detector with the CDRor have an exact or close replica. It may be more practical to use thesame circuitry. It is desirable to properly design the bandwidth of theadaptation loop such that it does not significantly affect theconvergence of the CDR loop. The adaptive loop is preferably designed sothat its bandwidth is slower than the bandwidth of the CDR. This allowsthe CDR to sample the data and output a phase that roughly samples atthe center of the data eye. The equalization is then updated at a lowerrate and slowly reduces the jitter due to such issues as backplaneattenuation.

FIG. 6 shows a block diagram for the digital adaptive scheme 300. Itincludes an equalizer filter 320 with a knob 322 (preferably implementedelectronically) to control the amount of boost. The output of theequalizer feeds a phase detector 330 used in the CDR to properly alignthe edges to sample data at the center of the eye. (BBPD stands forbang-bang phase detector, which is a digital phase detector instead of alinear phase detector. It is called bang bang because it is binary. Itoutputs a binary charge or discharge current based on the phaserelationship. It can also be tristate, but the width of the pulse is afixed period (vs. a linear phase detector which outputs a pulse widthproportional to the phase difference).) The phase detector 330 is fed byfour phases of clock running at half the rate of the data. The outputsof the phase detector 330 that feed the adaptive engine 340 are D0,DM01, D1, D1D, DM12, and D2.

FIG. 7 shows a diagram of the digital adaptation block 340. The inputsfrom the phase detector 330 are used by a pattern detector 410 and thedecision logic 420. The pattern detector 410 will latch the input andthen check if the pattern matches a predefined value (programmability ofthe pattern is desirable to allow a user to select what pattern(s) willbe used). The required pattern is preferably a series of CID followed bya transition. The pattern examples used in the earlier discussion hereinare 001 and 110. Of course, at a minimum, the pattern must include twosuccessive differently valued data bits because the equalizationdetermination is based on the timing of the transition between at leasttwo such successive bits. At the same time, the decision logic block 420also examines the latched data and outputs an UP or DN signal based onthe truth table given in FIG. 5 or whatever other control logic is beingemployed. An UP means that more boost is required, while a DN requiresreducing the boost. The decision update filter block 430 takes in the UPand DN signals as well as the detect signal. Based on this (e.g., block430 is only enabled to use an UP or DN signal when the detect signalindicates that the predetermined data sample pattern has been detected),block 430 outputs a digital code that feeds a D2A (digital to analog)conversion block 440. The D2A block 440 generates an analog output thatcontrols the amount of boost from the EQ (320 in FIG. 6). The decisionupdate filter block 430 also preferably performs some filtering (e.g.,integration over time) of the UP/DN/detect results and is able tocontrol the update rate (this is again preferably programmable so thatthe user can select, for example, how fast or slow equalizationadjustments are made). The update rate is preferably variable, because,as we mentioned earlier, the adaptation loop preferably runs slower thanthe CDR loop. One implementation is to have the decision update filter430 count the (net) number of UP or DN pulses when DETECT is assertedand increment (or decrement) Lvl [n:0] after “x” number of DETECTpulses.

Another possible (and desirable) feature is for the equalization to bepresettable. In many implementations the boost starts out at the minimumvalue. In the FIG. 1 prior art the amount of equalization is stored oncapacitors C1 and C2. The initial state of the capacitors is usually 0or a discharged condition. A presettable value is desirable because invery attenuated backplanes or other similar situations it may bepossible that a single bit may not have a transition. Thus it isrequired that a certain amount of boost be “preset” to allow veryattenuated bits to be boosted enough to be detected as a transition. TheReset/Preset pin allows presetting the output level of the D2A 440, aswell as reset the output of the pattern detector 410 so that adaptationdoesn't start until it is released.

There are many benefits and advantages to using the digital approach ofthis invention:

-   1. A digital approach allows easy migration from one technology to    the next. Analog circuits do not “like” to shrink and many circuits    may need to be redesigned. Digital circuits, on the other hand, run    faster as the process shrinks. This benefits a digital approach.-   2. The digital approach allows the adaptation circuitry to run as    fast as the phase detector and is not the limit in the overall    performance.-   3. The digital approach allows the actual updating of the loop to be    run at low speed. This can take a large burden off much of the    feedback loop. This is done via the decision update filter block    430.-   4. The digital approach has no requirements on transition density or    run length. An analog approach cannot tolerate data patterns that    don't have enough random frequency content. Additionally, very long    CID patterns would cause problems for an analog approach.-   5. The digital approach does not require the pattern to be DC    balanced. An analog approach uses filters and DC blocking capacitors    that can drift from the ideal operation if the pattern is not DC    balanced.

It will be understood that the foregoing is only illustrative of theprinciples of the invention, and that various modifications can be madeby those skilled in the art without departing from the scope and spiritof the invention. For example, the pattern of successive bits that isdetected as a pre-condition to performing a determination as to whethera transition in the data signal is relatively early or relatively latecan be of any desired length. Similarly, any number of UP/DN outputsignals of decision logic 420 can be integrated by decision updatefilter 430 prior to making a change in the signals that control theamount of equalization.

1. A method of equalizing a signal, the method comprising: receiving thesignal, the signal comprising a plurality of transition points;selecting a pattern of bits based, at least in part, on a convergencetime of the signal; detecting an occurrence of the pattern of bits inthe signal and identifying a transition point in the signal as the firsttransition point following the detected occurrence of the pattern ofbits; measuring a set of signal values associated with the firsttransition point; and adjusting an equalization level applied to thesignal based on the measured set of signal values.
 2. The method ofclaim 1, wherein the set of signal values comprises: a pre-transitionsample value, a transition sample value, and a post-transition samplevalue.
 3. The method of claim 1, further comprising classifying thesignal as either over equalized or under equalized based on the measuredset of signal values.
 4. The method of claim 1, wherein adjusting theequalization level comprises incrementing a boost value by a constantand predetermined amount.
 5. The method of claim 1, further comprisingextracting a timing signal from the signal.
 6. The method of claim 5,further comprising determining a time location for each signal value inthe set of signal values based on the timing signal.
 7. The method ofclaim 5, wherein the equalization level is adjusted at a rate slowerthan an update rate of a clock and data recovery loop.
 8. A systemcomprising: synchronization circuitry configured to: receive a signal,the signal comprising a plurality of transition points select a patternof bits based, at least in part, on a convergence time of the signal;detect an occurrence of the pattern of bits in the signal and identify atransition point in the signal as the first transition point followingthe detected occurrence of the pattern of bits; and measure a set ofsignal values associated with the first transition point; andequalization circuitry configured to adjust an equalization levelapplied to the signal based on the measured set of signal values.
 9. Thesystem of claim 8, wherein the set of signal values comprises: apre-transition sample value, a transition sample value, and apost-transition sample value.
 10. The system of claim 8, wherein theequalization circuitry is further configured to classify the signal aseither over equalized or under equalized based on the measured set ofsignal values.
 11. The system of claim 8, wherein the equalizationcircuitry is further configured to adjust the equalization level bydecrementing a boost value by a constant and predetermined amount. 12.The system of claim 8, wherein the synchronization circuitry is furtherconfigured to extract a timing signal from the signal.
 13. The system ofclaim 12, wherein the synchronization circuitry is further configured todetermine a time location for each signal value in the set of signalvalues based on the timing signal.
 14. The system of claim 12, whereinthe synchronization circuitry is further configured to adjust theequalization level at a rate slower than an update rate of a clock anddata recovery loop.
 15. A method of equalizing a data signal, the methodcomprising: receiving the data signal, the data signal representing aplurality of bits; determining a reference pattern of bits based, atleast in part, on a convergence time of the data signal; identifying aportion of the data signal as corresponding to bits that match thereference pattern; identifying a transition point in the data signal asthe first transition point following the identified portion of the datasignal; measuring a set of amplitude values associated with the firsttransition point; and equalizing the data signal based on the measuredset of amplitude values.
 16. The method of claim 15, wherein equalizingthe data signal comprises counting a number of over equalized samplesand a number of under equalized samples from the data signal.
 17. Themethod of claim 15, further comprising extracting a timing signal fromthe data signal.
 18. The method of claim 17, further comprisingdetermining time locations of a set of signal values based on the timingsignal.
 19. The method of claim 17, wherein the equalizing is performedat a rate that is determined in response to an update rate of a clockand data recovery loop.